The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A DSL communication system provides broadband digital communication over the traditional copper wiring that is used by the telephone network. Because DSL communication systems employ existing infrastructure they are an economically attractive solution to providing residential and commercial broadband service.
A version of DSL is described in the G.993.2 VDSL2 (Very high speed Digital Subscriber Line Transceivers 2) specification that is published by the International Telecommunication Union (ITU) and incorporated herein by reference in its entirety. VDSL2 describes in pertinent part a method for modulating data onto a plurality of carrier frequencies or tones that are carried over the copper wiring. Each tone has an associated signal-to-noise ratio and gain, which are referred to herein as the channel conditions. Each tone is modulated with a number of data bits that is based on the channel conditions associated with the tone. Each tone can therefore be modulated with a different number of bits. The number of bits is referred to as the bit loading. The bit loading of each tone is determined during an initialization sequence that is known to those skilled in the art. The material disclosed herein assumes that the bit loading has already been established for each tone.
Referring now to FIG. 1, a functional block diagram is shown of one of several embodiments of a VDSL2 communication system 10. Communication system 10 provides telephone and broadband communication services over copper wiring 12, which connects a customer location 14 to a telephone company switching station 16. Switching station 16 bridges copper wiring 12 to a broadband network 18 and a narrow-band network 20. An example of broadband network 18 such as the Internet. Examples of narrow-band networks 20 include Integrated Services Digital Network (ISDN) telephony and plain old telephone service (POTS). A high-pass filter 22 filters the VDSL2 tones to and from copper wiring 12 and a low-pass filter 24 filters ISDN or POTS signals to and from copper wiring 12.
A VDSL2 transceiver unit (VTU) or module 26 demodulates the tones that it receives from high-pass filter 22 and modulates the tones that it communicates to high-pass filter 22. Data that comes from broadband network 18 is processed by a Transport Protocol Specific—Transmission Convergence (TPS-TC) module 28 and a Physical Medium Specific—Transmission Convergence (PMS-TC) module 29. It then is processed by a trellis encoder module 31 and constellation mapper module 32. It then is converted by an analog front end (AFE) module 33 before reaching VTU 26. Data that comes from VTU 26 is converted by AFE module 33 and then is processed by a constellation unmapper module 34 and a trellis decoder module 35. It then is processed by a PMS-TC module 36 and a TPS-TC module 37 before reaching broadband network 18.
The configuration of the VDSL2 equipment at customer location 14 is similar to the configuration at switching station 16. Customer premises wiring 40 connects to copper wiring 12. A high-pass filter 42 filters the VDSL2 tones to and from premises wiring 40 and a low-pass filter 44 filters ISDN or POTS signals to and from premises wiring 40. Low-pass filter 44 filters the ISDN or POTS signals to/from a telephone set, voiceband modem, an ISDN channel, or the like. High-pass filter 42 filters the VDSL2 tones to/from a VTU 46. Data that comes from a home network 48 is processed through a TPS-TC module 50 and a PMS-TC module 51. It is then processed through a trellis encoder module 52 and a constellation mapper module 53. It is then processed through an AFE module 54 before reaching VTU 46. Data that comes from VTU 46 is processed through AFE module 54. It is then processed through a constellation unmapper module 55 and a trellis decoder module 56. It is then processed through a PMS-TC module 57 and a TPS-TC module 58 before reaching home network 48. Home network 48 provides networking connectivity between one or more pieces of customer provided equipment (CPE) 60, such as computers, printers, game consoles, voice over internet protocol (VOIP) telephones, digital televisions, and other such networked equipment.
Referring now to FIG. 2, a functional block diagram is shown of trellis encoder module 31. It should be noted that trellis encoder modules 31 and 50 operate similarly. An input at the left side of the block diagram receives a plurality of bits u1-uz, that are associated with two of the tones. The two tones are represented by the subscripts y and z. The number of received bits is between 1 and 15 for each tone and depends on the bit loading of each tone. Bit u1 is the least significant bit.
A convolutional encoder module 64 generates a bit u0 from bits u1 and u2. Bits u0-u2 are communicated to a mapper module 66 that implements Wei's 4D mapping algorithm. Mapper module 66 maps bits u0-u3 to four output bits w0, w1, v0, and v1. Mapper module 66 can employ the equations, w0=u2⊕u3, w1=u0⊕u1⊕u2⊕u3, v0=u3, and v1=u1⊕u3 to generate bits w0, w1, v0, and v1, respectively.
Referring now to FIG. 3, a functional block diagram is shown of an embodiment of convolutional encoder module 64. Bit u2 communicates with a first input of a first adder module 70. Bit u1 communicates with a first input of a second adder module 72. A first delay flip-flop 74 includes an input and an output that communicates with a second input of first adder module 70. The input of first delay flip-flop 74 communicates with an output of a fourth delay flip-flop 76. An output of first adder module 70 communicates with an input of a second delay flip-flop 78. An output of second delay flip-flop 78 communicates with an input of a third delay flip-flop 80 and a second input of second adder module 72. An output of third delay flip-flop 80 communicates with a third input of second adder module 72. An output of second adder module 72 communicates with an input of fourth delay flip-flop 76.
Trellis encoder module 31 is naturally suited to encode tones that have a bit loading of at least two because its convolutional encoder module 64 and mapper module 66 map the two least significant bits u1 and u2 to the four bits w0, w1 v0, and v1. Nonetheless, some DSL systems, such as ADSL2, ADSL2+, VDSL, and VDSL, collectively referred to as XDSL, allow a tone to have a bit loading of one.
Since trellis encoder module 31 needs at least two input bits, it cannot encode data for tones that have a bit loading of one. XDSL systems therefore employ a tone re-ordering scheme that pairs together tones that have a bit loading of one so that the data bits for the paired tones can be applied to trellis encoder module 31 and provide two input bits. The initialization sequence that assigns the bit loadings facilitates the tone reordering and pairing scheme by assuring that an even number of tones, if any, will have a bit loading of one. The tone reordering scheme is computationally intensive and uses memory to maintain several tone and bit loading tables. XDSL can employ up to a maximum of 4096 tones that are reordered by the tone reordering scheme.
Referring now to FIG. 4, a data diagram is employed to show the tone reordering scheme via an example that includes 23 tones. A tone ordering table t includes numbers that represent respective ones of the tones. The tones are ordered from left to right in the sequence that they will be transmitted. A bit allocation table b includes the bit loading of each tone as determined by the initialization sequence. The entries in table b are ordered by tone number, e.g. tone 1 has a bit loading of zero (i.e. the channel conditions are too poor to carry data), tone 2 has a bit loading of one, tone 3 has a bit loading of two, etc. In this example table b shows that tones 2, 6, 8, 13, 14, and 19 have a bit loading of one.
The tone reordering scheme generates a re-ordered tone table t′ based on tables t and b. Table t′ is formed by beginning with table t and moving the tones with a bit loading of one to the end of table t′. Moving the tones with a bit loading of one to the end of table t′ facilitates pairing those tones so that they can be applied to trellis encoder module 31.
The tone reordering scheme also generates a re-ordered bit table b′ based on tables t′ and b. Table b′ is formed by beginning with table b and pairing the bit loadings of one at the end of the table as shown at 80. The beginning of table b′ is padded with zeroes (the first three zeroes in this example) to backfill the bit loading spaces that were emptied by the paired bits. The zeroes from the table b are also moved to the beginning of table b′.
During normal operation or show time, trellis encoder module 31 receives the data bits that are associated with each tone. The data bits are applied to trellis encoder module 31 in the order that is shown in table t′, with an exception that the tones that have a bit loading of zero (e.g. tones 1, 9, 11, and 20 in this example) are ignored and not transmitted. At 82 the tones are shown in the order, left to right, that they are applied to the trellis encoder module 31. The bit loadings of each tone are shown at 84. The paired bit loads of one are indicated as a bit loading of 1+1. The tones with a bit loading of zero are shown in descended positions as placeholders for the purpose of explanation. It should be appreciated that tones with a bit loading of one are not actually applied to trellis encoder module 31.
Referring now to FIG. 5, a functional block diagram is shown of a pertinent part of an electronic circuit 100. Electronic circuit 100 includes a (b′, t′)-list generator module 102 and a bit application module 104. (b′, t′)-list generator module 102 executes computer instructions or software to generate the t′ and b′ tables. Bit application module 104 applies the user data, which will be carried over the tones, to trellis encoder module 31 in accordance with the bit loading. Bit application module 104 can be implemented with combinatorial and/or sequential logic.
(b′, t′)-list generator module 102 includes a processor 106, such as an ARM processor, that generates tables t′ and b′ based on tables t and b. Processor 106 also receives a bit swap signal 108 that indicates the t′ and b′ tables need to be updated because the b and t tables have changed. Processor 106 generates a sync info signal 110 that indicates when the t′ and b′ tables have been updated.
Bit application module 104 includes double buffers 112 that store the present values of tables t′ and b′ and copies of the updated values of tables t′ and b′. During normal operation or “show time”, bit application module 104 applies data to trellis encoder module 31 in accordance with the present t′ and b′ tables. Bit application module 104 replaces the present t′ and b′ tables with the updated t′ and b′ tables in accordance with sync info signal 110.
Processor 106 communicates the updated b′ and t′ tables to bit application module 104 via a communication bus 114. Tables t′ and b′ are about 4096 entries each, where each entry contains 12 bits of t′ to accommodate 4096 index and 4 bits of b′ to accommodate 0 to 15 possible bit load. The bandwidth of communication bus 114 therefore must be high enough to pass tables t′ and b′ without causing bit application module 104 to overflow and/or drop data. Communication bus 114 can therefore be implemented with a direct memory access (DMA) or other type of simple single read/write architecture. However, these architectures occupy a considerable die area in electronic circuit 100. Tables t, b, t′, and b′ also require a considerable amount of memory, which also requires die area. Processor 106 also employs scratchpad memory while generating tables t′ and b′, and the scratchpad memory also requires die area.